Shenzhen Hifibercom Technology Co.,Ltd QSFP28 ER4 Lite optical module
                     100G QSFP28 ER4 data 
sheet
                                                            100G QSFP28 ER4
Features
 Hot pluggable QSFP28 MSA form factor
 Compliant to Ethernet 100GBASE-ER4 Lite
 Supports 103.1Gb/s aggregate bit rate
 Up to 30km reach for G.652 SMF without 
FEC
 Up to 40km reach for G.652 SMF with FEC
 Single +3.3V power supply
 Operating case temperature: 0~70oC
 Transmitter: cooled 4x25Gb/s LAN WDM 
EML TOSA (1295.56, 1300.05, 1304.58, 
1309.14nm)
Applications
 Receiver: 4x25Gb/s APD ROSA
 100GBASE-ER4 Ethernet Links
 4x25G electrical interface (OIF CEI-28G-
 Infiniband  QDR  and  DDR
VSR)
interconnects
 Maximum power consumption 4.5W
 Client-side  100G  Telecom
 Duplex LC receptacle
Part Number Ordering Information
HFCCP-100G-ER QSFP28 ER4 Lite 30km optical transceiver with full real-time 
digital diagnostic monitoring and pull tab
1. General Description
This product is a 100Gb/s transceiver module designed for optical communication
applications compliant  to  Ethernet  100GBASE-ER4  Lite standard.  The  module
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converts 4 input channels of  25Gb/s electrical data to 4 channels of  LAN  WDM
optical  signals  and  then  multiplexes  them into  a  single  channel  for  100Gb/s
optical transmission. Reversely on the receiver side, the module de-multiplexes a
100Gb/s  optical  input  into  4  channels  of  LAN  WDM optical  signals  and  then
converts them to 4 output channels of electrical data.
The central  wavelengths  of  the  4  LAN WDM channels  are  1295.56, 1300.05,
1304.58 and 1309.14 nm as members of the LAN WDM wavelength grid defined
in  IEEE 802.3ba.  The high performance cooled LAN WDM EA-DFB transmitters
and high sensitivity APD receivers provide superior performance for 100Gigabit
Ethernet applications up to 30km links without FEC and 40km links with FEC.
The product is designed with form factor, optical/electrical connection and digital
diagnostic interface according to the  QSFP+  Multi-Source Agreement (MSA).  It
has been designed to meet the harshest external operating conditions including
temperature, humidity and EMI interference. 
2. Functional Description
The transceiver module receives 4 channels of 25Gb/s electrical data, which are
processed by a 4-channel Clock and Data Recovery (CDR) IC that reshapes and
reduces  the  jitter  of  each  electrical  signal.  Subsequently,  EML laser  driver  IC
converts each one of the 4 channels of electrical signals to an optical signal that
is transmitted from one of the 4 cooled EML lasers which are packaged in the
Transmitter Optical Sub-Assembly (TOSA). Each laser launches the optical signal
in specific wavelength specified in IEEE 802.3ba 100GBASE-ER4 requirements.
These 4-lane optical signals will be optically multiplexed into a single fiber by a 4-
to-1 optical WDM MUX. The optical output power of each channel is maintained
constant by an automatic power control (APC) circuit. The transmitter output can
be turned off by TX_DIS hardware signal and/or 2-wire serial interface.
The receiver receives 4-lane LAN WDM optical signals. The optical signals are de-
multiplexed by a 1-to-4 optical DEMUX and each of the resulting 4 channels of
optical  signals  is  fed into one of  the 4 receivers  that  are  packaged into  the
Receiver Optical Sub-Assembly (ROSA). Each receiver converts the optical signal
to an electrical signal.  The regenerated electrical  signals are retimed and de-
jittered and amplified by the RX portion of the 4-channel CDR.  The retimed 4-
lane  output  electrical  signals  are  compliant  with  CEI-28G-VSR interface
requirements. In addition, each received optical signal is monitored by the DOM
section. The monitored value is reported through the 2-wire serial interface. If
one or more received optical signal is weaker than the threshold level, RX_LOS
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hardware alarm will be triggered.
A single +3.3V power supply is required to power up this product. Both power
supply pins VccTx and VccRx are internally  connected and should be applied
concurrently. As per MSA specifications the module offers 7 low speed hardware
control pins (including the 2-wire serial interface): ModSelL, SCL, SDA, ResetL,
LPMode, ModPrsL and IntL.
Module Select (ModSelL) is an input pin. When held low by the host, this product
responds to 2-wire serial communication commands. The ModSelL allows the use
of this product on a single 2-wire interface bus – individual ModSelL lines must be
used.
Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus
communication  interface and enable the  host  to  access the  QSFP28 memory
map.
The Reset L pin enables a complete reset, returning the settings to their default
state, when a low level on the Reset L pin is held for longer than the minimum
pulse length. During the execution of a reset the host shall disregard all status
bits until it indicates a completion of the reset interrupt. The product indicates
this by posting an IntL (Interrupt) signal with the Data Not Ready bit negated in
the memory map. Note that on power up (including hot insertion) the module
should post this completion of reset interrupt without requiring a reset.
Low Power Mode (LP Mode) pin is used to set the maximum power consumption
for the product in order to protect hosts that are not capable of cooling higher
power modules, should such modules be accidentally inserted.
Module  Present  (Mod  PrsL)  is  a  signal  local  to  the  host  board  which,  in  the
absence of a product, is normally pulled up to the host Vcc. When the product is
inserted into the connector, it completes the path to ground through a resistor on
the host  board and asserts  the signal.  ModPrsL then indicates its  present by
setting ModPrsL to a “Low” state.
Interrupt (Int L) is an output pin. “Low” indicates a possible operational fault or a
status critical to the host system. The host identifies the source of the interrupt
using the 2-wire serial interface. The IntL pin is an open collector output and
must be pulled to the Host Vcc voltage on the Host board.
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3. Transceiver Block Diagram
Figure 1.  Transceiver Block Diagram
4. Pin Assignment and Description
Figure 2.  MSA compliant Connector
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Pin Definition
Note
PIN Logic Symbol Name/Description
s
1   GND Ground 1
2 CML-I Tx2n Transmitter Inverted Data Input
3 CML-I Tx2p Transmitter Non-Inverted Data output
4   GND Ground 1
5 CML-I Tx4n Transmitter Inverted Data Input
6 CML-I Tx4p Transmitter Non-Inverted Data output
7   GND Ground 1
8 LVTLL-I ModSelL Module Select
9 LVTLL-I ResetL Module Reset
10   VccRx +3.3V Power Supply Receiver 2
11 LVCMOS-I/O SCL 2-Wire Serial Interface Clock
12 LVCMOS-I/O SDA 2-Wire Serial Interface Data
13   GND Ground
14 CML-O Rx3p Receiver Non-Inverted Data Output
15 CML-O Rx3n Receiver Inverted Data Output 
16   GND Ground 1
17 CML-O Rx1p Receiver Non-Inverted Data Output 
18 CML-O Rx1n Receiver Inverted Data Output 
19   GND Ground 1
20   GND Ground 1
21 CML-O Rx2n Receiver Inverted Data Output 
22 CML-O Rx2p Receiver Non-Inverted Data Output 
23   GND Ground 1
24 CML-O Rx4n Receiver Inverted Data Output 1
25 CML-O Rx4p Receiver Non-Inverted Data Output 
26   GND Ground 1
27 LVTTL-O ModPrsL Module Present 
28 LVTTL-O IntL Interrupt 
29   VccTx +3.3 V Power Supply transmitter 2
30   Vcc1 +3.3 V Power Supply 2
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31 LVTTL-I LPMode Low Power Mode 
32   GND Ground 1
33 CML-I Tx3p Transmitter Non-Inverted Data Input 
34 CML-I Tx3n Transmitter Inverted Data Output 
35   GND Ground 1
36 CML-I Tx1p Transmitter Non-Inverted Data Input 
37 CML-I Tx1n Transmitter Inverted Data Output 
38   GND Ground 1
    Notes:
1. GND is the symbol  for  signal  and supply  (power)  common for the QSFP28
module.  All  are  common  within  the  module  and  all  module  voltages  are
referenced to this potential unless otherwise noted. Connect these directly to
the host board signal common ground plane.
2.  VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers
and shall  be applied concurrently.  Recommended host board power supply
filtering is shown in Figure 3 below. Vcc Rx, Vcc1 and Vcc Tx may be internally
connected within the module in any combination. The connector pins are each
rated for a maximum current of 1000mA.
5. Recommended Power Supply Filter
Figure 3. Recommended Power Supply Filter
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6. Absolute Maximum Ratings
It has to be noted that the operation in excess of any individual absolute 
maximum ratings might cause permanent damage to this module. 
Symb Unit Note
Parameter ol Min Max s s
Storage Temperature  TS -40 85 degC
Operating Case Temperature  TOP 0 70 degC
Power Supply Voltage  VCC -0.5 3.6 V
Relative Humidity (non-condensation) RH 0 85 %
Damage Threshold, each Lane THd -3.0 dBm
7. Recommended Operating Conditions and Power Supply Requirements
Symb Unit Note
Parameter Min Typical Max
ol s s
deg
Operating Case Temperature TOP 0 70
C
3.13 3.46
Power Supply Voltage VCC 3.3 V
5 5
25.7812
Data Rate, each Lane Gb/s
5
Data Rate Accuracy -100 100 ppm
Control Input Voltage High 2 Vcc V
Control Input Voltage Low 0 0.8 V
Link Distance with G.652 (without 
D1 30 km 1
FEC)
Link Distance with G.652 (with 
D2 40 km 1
FEC)
Notes:
1. Depending on actual fiber loss/km (link distance specified is for fiber insertion loss
of 0.4dB/km)
8. Electrical Characteristics
The  following  electrical  characteristics  are  defined  over  the  Recommended
Operating Environment unless otherwise specified. 
Parameter Test Min Typic Max Units Notes
Point al
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Power Consumption 4.5 W
Supply Current Icc 1.36 A
Transmitter (each Lane)
Overload Differential 
TP1a 900 mV
Voltage pk-pk
Common Mode Voltage 
TP1 -350 2850 mV 1
(Vcm)
Differential Termination At
TP1 10 %
Resistance Mismatch 1MHz
See CEI-
Differential Return Loss 28G-VSR
TP1 dB
(SDD11) Equatio
n 13-19
Common Mode to 
Differential conversion See CEI-
and Differential to 28G-VSR
TP1 dB
Common Mode Equatio
conversion (SDC11, n 13-20
SCD11)
See CEI-
28G-VSR
Stressed Input Test TP1a Section
13.3.11.2
.1
Receiver (each Lane)
Differential Voltage, pk-pk TP4 900 mV
Common Mode Voltage 
TP4 -350 2850 mV 1
(Vcm)
Common Mode Noise, 
TP4 17.5 mV
RMS
Differential Termination At
TP4 10 %
Resistance Mismatch 1MHz
Differential Return Loss TP4 See CEI- dB
(SDD22) 28G-VSR
Equatio
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n 13-19
Common Mode to 
Differential conversion See CEI-
and Differential to 28G-VSR
TP4 dB
Common Mode Equatio
conversion (SDC22, n 13-21
SCD22)
Common Mode Return 
TP4 -2 dB 2
Loss (SCC22)
Transition Time, 20 to 
TP4 9.5 ps
80%
Vertical Eye Closure (VEC) TP4 5.5 dB
Eye Width at 10-15 
TP4 0.57 UI
probability (EW15)
Eye Height at 10-15 
TP4 228 mV
probability (EH15)
Notes:
2. Vcm is generated by the host. Specification includes effects of ground offset 
voltage.
3. From 250MHz to 30GHz.
9. Optical Characteristics
Ethernet 100GBASE-ER4 Lite
Symbo
Parameter Min Typical Max Units Notes
l
1294.5 1295.5 1296.5
L0 nm
3 6 9
1299.0 1300.0 1301.0
L1 nm
2 5 9
Lane Wavelength
1303.5 1304.5 1305.6
L2 nm
4 8 3
1308.0 1309.1 1310.1
L3 nm
9 4 9
Transmitter
SMSR SMSR 30 dB
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Total Average Launch Power PT 10.5 dBm
Average Launch Power,
PAVG -2.9 4.5 dBm 1
each Lane
OMA, each Lane POMA 0.1 4.5 dBm 2
Difference in Launch Power 
between any Two Lanes Ptx,diff 3.6 dB
(OMA)
Launch Power in OMA minus 
Transmitter and Dispersion -0.65 dBm
Penalty (TDP), each Lane
TDP, each Lane TDP 2.5 dB
Extinction Ratio ER 7 dB
RIN20OMA RIN -130 dB/Hz
Optical Return Loss Tolerance TOL 20 dB
Transmitter Reflectance RT -12 dB
Average Launch Power OFF 
Poff -30 dBm
Transmitter, each Lane
Eye Mask{X1, X2, X3, Y1, Y2, {0.25, 0.4, 0.45, 0.25,
Y3} 0.28, 0.4}
Receiver
Damage Threshold, each 
THd -3.0 dBm 3
Lane
for
30km
Average Receive Power, each
-16.9 -4.9 dBm Link
Lane
Distanc
e
for
40km
Average Receive Power, each
-20.9 -4.9 dBm Link
Lane
Distanc
e
Receive Power (OMA), each 
-1.9 dBm
Lane
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for  BER
Receiver Sensitivity (OMA), 
SEN1 -14.65 dBm = 1x10-
each Lane
12
for  BER
Stressed Receiver Sensitivity
(OMA), each Lane -12.65 dBm = 1x10
-
12
for  BER
Receiver Sensitivity (OMA), 
SEN2 -18.65 dBm = 5x10-
each Lane
5
for  BER
Stressed Receiver Sensitivity
(OMA), each Lane -16.65 dBm = 5x10
-
5
Receiver reflectance -26 dB
Difference in Receive Power 
between any Two Lanes Prx,diff 3.6 dB
(Average and OMA)
LOS Assert LOSA -26 dBm
LOS Deassert LOSD -24 dBm
LOS Hysteresis LOSH 0.5 dB
Receiver Electrical 3 dB 
upper Cutoff Frequency, Fc 31 GHz
each Lane
Conditions of Stress Receiver Sensitivity Test (Note 4)
Vertical Eye Closure Penalty, 
1.5 dB
each Lane
Stressed Eye J2 Jitter, each 
0.3 UI
Lane
Stressed Eye J9 Jitter, each 
0.47 UI
Lane
Notes:
1. The minimum average launch power spec is based on ER not exceeding 9.5dB
and transmitter OMA higher than 0.1dBm.
2. Even if the TDP < 0.75 dB, the OMA min must exceed the minimum value 
specified here.
3. The receiver shall be able to tolerate, without damage, continuous exposure 
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to a modulated optical input signal having this power level on one lane. The 
receiver does not have to operate correctly at this input power.
4. Vertical eye closure penalty, stressed eye J2 jitter, and stressed eye J9 jitter 
are test conditions for measuring stressed receiver sensitivity. They are not 
characteristics of the receiver.
10. Digital Diagnostic Functions
The following digital diagnostic characteristics are defined over the normal 
operating conditions unless otherwise specified. 
Parameter Symbol Min Max Units Notes
Temperature monitor Over operating
absolute error DMI_Temp -3 +3 degC temperaturerange
Supply voltage Over full
monitor absolute DMI _VCC -0.1 0.1 V
error operating range
Channel RX power 
monitor absolute DMI_RX_Ch -2 2 dB 1
error
Channel Bias current DMI_Ibias_C -10% 10% mA
monitor h
Channel TX power 
monitor absolute DMI_TX_Ch -2 2 dB 1
error
Notes:
1. Due to measurement accuracy of different single mode fibers, there could be an additional +/-1 dB
fluctuation, or a +/- 3 dB total accuracy.
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11.  Mechanical Dimensions
        Figure 4. Mechanical Outline
12. ESD 
This transceiver is specified as ESD threshold  1kV for  SFI pins and 2kV for  all
other electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-
A (HBM). However, normal ESD precautions are still required during the handling
of this module. This transceiver is shipped in ESD protective packaging. It should
be  removed  from  the  packaging  and  handled  only  in  an  ESD  protected
environment.   
13. Laser Safety
This  is  a  Class  1  Laser  Product  according  to  EN  60825-1:2014.  This  product
complies with 21 CFR 1040.10 and 1040.11 except for deviations pursuant to
Laser Notice No. 50, dated (June 24, 2007).
Caution: Use of controls or adjustments or performance of procedures other than
those specified herein may result in hazardous radiation exposure.
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Contact Information
Shenzhen Hifibercom Technology Co., Ltd
Factory Add : A8 First  Floor  Silicon Valley Power, Longhua District,  Shenzhen,
China 518040
Tel:+86(0)0755- 2107 4669
Fax:+86(0)0755-2107 4669
Email:[email protected]
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