Die-to-Die IP Subsystem
                     Die-to-Die IP Subsystem
• Die-to-Die IP Subsystem Die-to Die IP Subsystem offers a unique value proposition in 
terms of low power, high throughput, and low latency links enabling faster time to 
integration for heterogenous chipset connections in wired communications, AI and 
HPC applications
• Die-to-Die IP Subsystem is targeted for heterogenous chiplet solutions in wired 
communications, AI and HPC applications. With recent advances in package 
technologies, it is possible to route high-speed signals within a package connecting 
multiple dies either on Interposer or on Organic Substrate. 
• Die-to-Die IP Subsystem offers a unique value proposition in terms of low power, high 
throughput and low latency links enabling faster time to integration.
https://openfive.com/die-to-die-ip-subsystem/
Block Diagram
      Die-to-Die IP Subsystem is targeted for heterogenous chiplet solutions in 
wired communications, AI and HPC applications. With recent advances in 
package technologies, it is possible to route high-speed signals within a 
package connecting multiple dies either on Interposer or on Organic 
Substrate.
 
https://openfive.com/die-to-die-ip-subsystem/
D2D Controller IP
 D2D Controller IP Key Features
• Ultra-high-bandwidth and performance (For e.g. 1024-bit AXI interface at 2GHz can provide up 
to 2 Tbps)
• Ultra-low latency including Tx and Rx depending on the optional FEC module to improve BER
• Support for the SerDes rates up to 112 Gbps (CEI-112G-XSR) and aggregation support up to 48 
lanes
• Independent SerDes lane enable/disable and fully programmable SerDes lane mapping
• Flexible AXI interface options including 64b, 128b, 256b, 512b and 1024b
• Optional In-band and Out-of-Band flow control
• Built-in error detection and interrupt structure
• Optional re-transmission module for error free transmission
• Configurable error injection mechanisms for testability
• Debug Features: PRBS generators/checkers and loopback support for both data and flow control
https://openfive.com/die-to-die-ip-subsystem/
D2D PHY IP
    D2D PHY IP Key Features
• D2D PHY signals are single ended (Single Duplex) and are based on HBM Memory 
Electrical IOs
• Each channel is made up of 42 pairs of Tx/Rx signals that runs at configurable 
speed up to 16Gbps contributing up to ~1.75Tbps/mm
• Channel lengths support up to 5mm with latency less than 5ns (Other 
combinations are available)
• Best in the industry less than 0.5 pJ/bit power consumption
• Built-in PLL to support differential clock forwarding
• Self-contained initialization and calibration state machines
• No requirement of Forward Error Correction (FEC) IP as signal supports channel 
BER up to 1E-21
• Programmable output drivers
• Compatible to various parallel wire specification in the industry
https://openfive.com/die-to-die-ip-subsystem/
Please do visit my website for 
in-depth information.
Website: 
https://openfive.com/die-to-die-ip-subsystem/