IP Portfolio-Connectivity IP-IP for High Performance Computing-IP Integration in SoC
                     IP Portfolio
• Differentiate using our customizable SoC IP Best-in-class SoC IPs cover a wide range of 
applications from Embedded, AI, Networking to Enterprise markets.
• Interlaken IP Subsystem High speed chip-to-chip interface protocol with scalable 
bandwidth, low latency and reliable data transfer over serial links. 
• Die-to-Die IP Subsystem Die-to Die IP Subsystem offers a unique value proposition in 
terms of low power, high throughput, and low latency links enabling faster time to 
integration for heterogenous chipset connections in wired communications, AI and 
HPC applications
• USB IP Subsystem Full range of USB controllers supporting USB 2.0 / USB 3.0 / USB 3.1 
gen1 and gen2 in host and device mode of operation. Supports AXI interface and in-
built DMA features.
https://openfive.com/ip/
Interlaken IP Subsystem
• High speed chip-to-chip interface protocol with scalable bandwidth, low 
latency and reliable data transfer over serial links. 
• Interlaken IP is used by many applications including NPU, traffic 
management and switch fabrics. 
https://openfive.com/ip/
Die-to-Die IP Subsystem
• Die-to Die IP Subsystem offers a unique value proposition in terms of low 
power, high throughput, and low latency links enabling faster time to 
integration for heterogenous chipset connections in wired 
communications, AI and HPC applications
https://openfive.com/ip/
USB IP Subsystem
• SiFive provides a complete portfolio of USB-certified controllers with host 
and device functionality.
• They are integrated with our PHY partners in multiple foundries and 
nodes. FPGA boards are available for demo and prototype use.
https://openfive.com/ip/
Please do visit my website for 
in-depth information.
Website: 
https://openfive.com/ip/